1. Field of the Invention
The present invention relates to a method for manufacturing passive components, and more particularly, to a method of integrating the manufacturing processes of passive components.
2. Description of the Prior Art
Recently, the integrated circuit (IC) industry has developed continuously and flourishingly. The IC products, such as memory chips and central processing unit (CPU) chips that are popular from the early stage and communication chips that are popular and widely utilized in the age of mobile communication, are all developed toward powerful functions, low price, and small size. In other words, the integration process of passive components, such as the capacitors or the inductances in the chip, becomes a great challenge for circuit designs. Traditionally, when interconnects of an integrated circuit are manufactured, the needed inductance structures or capacitor structures are formed simultaneously according to the circuit design. In the light of the manufacturing process, the designed metal pattern is first transferred to a metal layer by utilizing the lithographic process, and the needed passive components and interconnects are manufactured subsequently by utilizing the processes, such as an etching process and a photoresist striping process.
Please refer to FIG. 1 through FIG. 7. FIG. 1 through FIG. 7 are schematic diagrams illustrating a method for forming a capacitor 36, an inductance structure 12 and an outer connecting pad 52 in a semiconductor wafer 30 according to the prior art. As shown in FIG. 1, a semiconductor wafer 30 is provided first. The semiconductor wafer 30 includes a substrate 10, and a first dielectric layer 14 covering the substrate 10. It should be noted that the semiconductor wafer 30 includes an inner core circuit (the full view of the inner core circuit is not shown in the figures), which includes a plurality of transistor components, a plurality of resistance components, a plurality of interconnects etc., so as to electrically connect to the follow-up capacitor structure, the follow-up inductance structure, the follow-up outer connecting pad and other components in the semiconductor wafer 30. However, the detailed connection of the inner core circuit depends on the chip design, and is not described in detail here. Subsequently, an inductance pattern opening 22 and a plug hole 66 are formed in the first dielectric later 14 by utilizing an etching process. As shown in FIG. 2, a copper layer is thereafter formed to fill the inductance pattern opening 22 and the plug hole 66. The filling copper layer in the inductance pattern opening 22 becomes an inductance structure 12, and the inductance structure 12 is electrically connected to the interconnect of the substrates 10 below. The filling copper layer in the plug hole 66 becomes a plug 17, and the plug 17 is a part of the interconnect of the semiconductor wafer 30.
Next, as shown in FIG. 3, an isolation layer 16 is formed on a surface of the wafer 10. The isolation layer 16, being a silicon nitride layer, covers the inductance structure 12 to prevent copper atoms in the inductance structure 12 from diffusing upwards. A first conductive layer 18 is thereafter formed on a surface of the isolation layer 16. The first conductive layer 18 comprises a tantalum nitride layer (TaN layer) or a titanium nitride layer (TiN layer), and the first conductive layer 18 is formed by a sputtering process. After that, a first patterned photoresist layer 24 is formed on the first conductive layer 18 by utilizing a coating process and a photolithography process to define a bottom electrode pattern.
As shown in FIG. 4, an etching process is furthermore performed to etch the first conductive layer 18 until reaching the surface of the isolation layer 16, by utilizing the first patterned photoresist layer 24 as an etching mask, to form a bottom electrode 26 of capacitor. After that, as shown in FIG. 5, a deposition process is performed after removing the first patterned photoresist layer 24 to form an insulating layer 28 on the surface of the wafer 10. The insulating layer 28 includes a silicon oxide layer or a silicon nitride layer, and the insulating layer 28 covers the bottom electrode 26. A second conductive layer 32 is next formed on a surface of the insulating layer 28. The second conductive layer 32 includes a tantalum nitride layer or a titanium nitride layer, and the second conductive layer 32 is formed by another sputtering process. A second patterned photoresist layer 34 is thereafter formed on the second conductive layer 32 to define a top electrode pattern.
As shown in FIG. 6, another etching process is next performed to etch the second conductive layer 32 and the insulating layer 28 until reaching the surface of the first conductive layer 18, by utilizing the second patterned photoresist layer 34 as an etching mask, to form a top electrode 38 and a capacitor dielectric layer 42 of the capacitor 36. The fabrication of the capacitor 36 is thus completed. As shown in FIG. 7, another deposition process is thereafter performed, after removing the second patterned photoresist layer 34, to form a second dielectric layer 44 on the surface of the wafer 10. The second dielectric layer 44 covers the capacitor 36. After that, an interconnecting process is performed to form a plug 46 in the second dielectric layer 44. Next, an outer connecting pad 52 is formed on the plug 46 by utilizing the processes, such as a sputtering process and an etching process. The outer connecting pad 52 is usually an aluminum pad (Al pad), which is electrically connecting to some components of the semiconductor wafer 30 through the interconnects of the semiconductor wafer 30, used for electrically connecting to an external device. It is worthy of note that the inductance structure 12, the capacitor 36, the plugs 17, 46 and other components in the semiconductor wafer 30 that are manufactured before the outer connecting pad 52 are all parts of the inner core circuit in the semiconductor wafer 30.
The prior art method of forming the passive components requires at least four photo masks to define the shape of the capacitor, the shape of the inductance and the position of the outer connecting pad. That means, at least four photolithography processes and at least four etching processes are required, making the processing very long. The cost is thus raised. In addition, the yield is sometimes decreased due to complex process steps used to affect the performance of the formed chip. The top electrode and the bottom electrode of the capacitor might even get higher resistance due to the prior art method of manufacturing the passive components, and cause the quality factor (Q factor) of the capacitor to decrease.